As known, a phase-locked loop (PLL) circuit can provide an accurate oscillation signal. Consequently, the phase-locked loop circuit is wirelessly used in a wireless communication system.
FIG. 1 is a schematic circuit diagram illustrating a conventional phase-locked loop circuit. As shown in FIG. 1, the phase-locked loop circuit 100 comprises a phase frequency detector (PFD) 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator (VCO) 140 and a feedback circuit 150.
The phase frequency detector 110 receives a reference signal Sref and a feedback signal Sfb, and generates a control signal Sctrl.
The charge pump 120 comprises a charging path and a discharging path. A charging current with a magnitude Kpup is provided by the charging path. A discharging current with a magnitude Kpdn is provided by the discharging path. Moreover, the charge pump 120 receives the control signal Sctrl. According to the control signal Sctrl, a switch Swu in the charging path or a switch Swd in the discharging path is selectively turned on to generate a driving current Ic to the loop filter 130. In case that the switch Swu is turned on according to the control signal Sctrl, the driving current Ic is the charging current with the magnitude Kpup. In case that the switch Swd is turned on according to the control signal Sctrl, the driving current Ic is the discharging current with the magnitude Kpdn.
The loop filter 130 comprises an RC circuit. According to the driving current Ic from the charge pump 120, a charge/discharge control operation is performed on the RC circuit. Consequently, the loop filter 130 generates a tuned voltage Vtune to the voltage controlled oscillator 140. The RC circuit comprises two serially-connected resistors and a capacitor C. The resistance of each resistor is 2Rp. That is, the equivalent resistance of the loop filter 130 is equal to Rp.
The voltage controlled oscillator 140 receives the tuned voltage Vtune and generates an oscillation signal Sosc. As shown in FIG. 1, the voltage controlled oscillator 140 comprises a variable capacitance device 142. The variable capacitance device 142 receives the tuned voltage Vtune. When the tuned voltage Vtune is changed, the equivalent capacitance of the variable capacitance device 142 is correspondingly changed. Consequently, the frequency of the oscillation signal Sosc is changed.
The feedback circuit 150 comprises a frequency divider 152. The frequency divider 152 receives the oscillation signal Sosc and performs a frequency division on the oscillation signal Sosc. Consequently, the feedback signal Sfb is outputted from the frequency divider 152 to the phase frequency detector 110.
For assuring normal operations of the phase-locked loop circuit 100, it is important to calibrate the phase-locked loop circuit 100. During the calibrating process, it is necessary to calibrate the driving current Ic of the charge pump 120, the RC time constant of the loop filter 130 and the VCO gain Kvco of the voltage controlled oscillator 140. Generally, the calibrating process can be performed when the phase-locked loop circuit 100 is in an open-loop state or a closed-loop state.
For example, U.S. Pat. No. 8,483,985 discloses a PLL loop bandwidth calibration method. In addition, U.S. Pat. No. 8,421,507 discloses a phase-locked loop with a calibration function and an associated calibration method.